20 annunci per il ruolo di embedded senior engineer (recruiting in corso)

Senior Formal Verification Engineer
TechBiz Global GmbH —Bolzano - Bozen, Trentino-Alto Adige
- Tempo pieno
- Remoto
- Microsoft Word
- Dottorato di ricerca
- Laurea triennale
Candidatura rapida
Senior Software Engineer C/C++/C#
Inpeco —Val della Torre, Piemonte
- Remoto
- Informatica
- Informatica
- C++
Candidatura rapida
Firmware Engineer
TechBiz Global GmbH —Bolzano - Bozen, Trentino-Alto Adige
- Tempo pieno
- Gestionale
- Competenze analitiche
- C++
Candidatura rapida
Engineer, Embedded Software
Dana Incorporated —Rivoli, Piemonte
- Azure
- DevOps
- Ingegneria
Senior Validation Engineer
Renesas Electronics —Catania, Sicilia
- 37.000 € - 60.000 € all'anno
- Tempo pieno
- Gestionale
- Inglese
- Laurea magistrale
Candidatura rapida
Senior Forward Deployed Engineer, Italian Speaking
Salesforce —Roma, Lazio
- 56.325 € - 75.375 € all'anno
- Tempo pieno
- Informatica
- Salesforce
- DevOps
Motorsport R&D Embedded Firmware Senior Engineer
Marelli —Venaria Reale, Piemonte
- 40.000 € - 60.000 € all'anno
- Inglese
- C++
- Python
Principal Forward Deployed Engineer, Italian Speaking
Salesforce —Milano, Lombardia
- 88.200 € - 117.900 € all'anno
- Tempo pieno
- Informatica
- Salesforce
- DevOps
Software Functional Safety Senior Engineer
STMicroelectronics —Agrate Brianza, Lombardia
- 55.000 € - 70.000 € all'anno
- Informatica
- Laurea magistrale
1 giorno
Senior Application Engineer for Automotive Microcontroller – Rapid Response (f/m/div)
Infineon Technologies AG —Padova, Veneto
- 38.320 € - 52.690 € all'anno
- Inglese
- Sviluppo software
10 giorni
System Engineer
Officina Stellare —Vicenza, Veneto
- 45.000 € - 55.000 € all'anno
- Tempo pieno
- Parzialmente remoto
- Gestionale
- Ingegneria
- Inglese
Robotics Engineer/Staff Software Engineer - Arduino, Turin, Italy
Qualcomm —Torino, Piemonte
- Remoto
- Gestionale
- Dottorato di ricerca
- CAD
Senior Motor Control Engineer
FlyingBasket —Bolzano - Bozen, Trentino-Alto Adige
- Tempo pieno
- Inglese
- C++
Principal Test Engineer
Renesas Electronics —Catania, Sicilia
- 74.000 € - 100.000 € all'anno
- Tempo pieno
- Remoto
- Gestionale
- Laurea magistrale
- C++
Candidatura rapida
Digital Design Engineer - Senior/Staff/Principal
Inventvm Semiconductor —Pavia, Lombardia
- Tempo pieno
- Dottorato di ricerca
- Ingegneria
- Inglese
Senior Firmware and Control Engineer
Vertiv —Bologna, Emilia-Romagna
- 41.000 € - 52.000 € all'anno
- Tempo pieno
- Inglese
- Maturità
- Laurea triennale
Digital Design Engineer - Junior/Senior
Inventvm Semiconductor —Pavia, Lombardia
- Tempo pieno
- Dottorato di ricerca
- Ingegneria
- Inglese
Junior Embedded Software & Cybersecurity Engineer
Consilium Safety —Vecchiano, Toscana
- Informatica
- Sviluppo software
Product Expert, Fendt
AGCO —Breganze, Veneto
- 40.000 € - 50.000 € all'anno
- Remoto
- Ingegneria
- Inglese
Senior EmbeddedSoftware Engineer
TechBiz Global GmbH —Roma, Lazio
- Tempo pieno
- Laurea magistrale
- C++
- Laurea triennale
Candidatura rapida

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Senior Formal Verification Engineer

TechBiz Global GmbH
Bolzano - Bozen, Trentino-Alto Adige

Candidatura rapida

Dettagli della posizione

Tempo pieno

Qualifiche

Microsoft Word
Dottorato di ricerca
Bash
Laurea triennale
Hardware del computer
Ingegneria elettrica
Python

Descrizione completa della posizione

At TechBiz Global, we are providing recruitment service to our TOP clients from our portfolio. We are currently seeking a Senior Formal Verification (FV) Engineer to join one of our clients' teams.

Reporting directly to the Vector Unit Verification Lead, this is a highly technical Individual Contributor (IC) role. In this position, you will be the dedicated formal expert for the VU team, responsible for designing scalable formal testbenches, writing mathematical properties, and ensuring the absolute algorithmic and architectural integrity of our vector pipeline. You will work side-by-side with VU microarchitects to hunt down deep corner-case bugs and achieve formal sign-off on high-complexity arithmetic and execution blocks.

Key Responsibilities

Block-Level Execution & Convergence Engineering (90%)

End-to-End Testbench Ownership: Design, deploy, and maintain robust formal verification environments for complex Vector Unit sub-blocks (e.g., Vector Execution Pipelines, Vector Register File/Rename interfaces, and Vector Floating-Point Units).
Datapath & Arithmetic Verification: Implement advanced word-level modeling, bit-blasting, and algebraic rewriting strategies to verify complex IEEE-754 floating-point and integer vector arithmetic units.
Proof Convergence Management: Independently diagnose and resolve proof-convergence failures, over-constraints, and state-space explosions using advanced reduction techniques (e.g., case-splitting, black-boxing, and abstraction modeling).
RISC-V Vector Compliance: Develop formal environments to mathematically prove that the VU pipeline strictly complies with the RISC-V Vector (V) Extension specification.
Simulation Partnership: Collaborate closely with VU simulation engineers to define a razor-sharp boundary between simulation and formal verification, ensuring maximum bug-hunting efficiency and zero coverage gaps.

Embedded Mentorship & Best Practices (10%)

Formal-Friendly Design: Partner with VU microarchitects during early-stage RTL development to drive formal-friendly coding styles and structural design patterns.
SVA Propagation: Review and refine SystemVerilog Assertions (SVA) written by design and simulation peers, establishing best practices for block-level assertions within the VU team.

Education: B.S./M.S. in Computer Engineering, Electrical Engineering, or Computer Science with practical industry execution; or a Ph.D. with a research focus on formal methods or computer arithmetic.
Experience: 5+ years of production-grade hardware verification experience (or Ph.D. + 1–3 years) with a strong, proven track record of applying formal verification to CPU, GPU, or DSP execution pipelines.
Collaboration Style: A self-driven engineer who enjoys deep mathematical puzzles, collaborates seamlessly within a localized block-level team, and can translate complex proof counter-examples into actionable bugs for designers.
Datapath Validation Focus: Strong specialization in arithmetic formal verification, algebraic rewriting, and word-level modeling. Familiarity with control-path formal techniques (liveness, safety properties) is highly welcome.
Vector Microarchitecture: Good working knowledge of high-width execution pipelines, vector execution units, or floating-point/integer arithmetic hardware. Experience with Out-of-Order execution mechanics is a plus.
Formal Tools: Proficient command of commercial EDA formal tools (e.g., Cadence JasperGold/DPV, Synopsys VC Formal, Siemens OneSpin) and their specialized mathematical/datapath apps.
Languages: Native fluency in SystemVerilog and SystemVerilog Assertions (SVA). Scripting proficiency (Python, Tcl, or Bash) for testbench automation.

Nice to Have

RISC-V Core Verification.
RISC-V Ecosystem: Familiarity with the RISC-V Architecture, specifically the Vector (V) and Floating-Point (F/D) extension ecosystems.
Emulation platforms (Veloce, ZeBu).
Core/Bus interface protocols (e.g., AXI/CHI).

Candidatura rapida

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