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Senior Digital IC Design Engineer

Ferroelectric Memory GmbH
Agrate Brianza, Lombardia

Candidatura rapida

Dettagli della posizione

Tempo pieno

Qualifiche

Inglese
Ingegneria elettrica
Debugging

Descrizione completa della posizione

Role Overview

In this role, you will lead the architecture, design, and implementation of digital memory chips that combine digital, logic, NVM analog circuitry, and high‑speed interfaces. You will be involved throughout the full development cycle, from specification and RTL design through functional and physical verification, all the way to post‑silicon validation, working closely with the analog and layout teams in a fast‑moving start‑up environment.

Responsibilities

Design and develop emerging NVM memory devices based on Hafnium Oxide technology, contributing to innovative memory architectures.
Support the design team in defining specifications and integrating digital and analog blocks into the complete memory system.
Own the architecture, design, and implementation of digital memory chips, including integration of NVM analog circuits, logic buses, and external/internal interfaces.
Run functional verification (simulation, regression, coverage) to ensure robust, sign‑off‑quality designs.
Collaborate closely with analog design and layout engineers to ensure chip robustness, timing closure, and area/power optimization.
Perform post‑silicon verification and debug, correlating lab measurements with simulation results and driving design improvements.

Your profile

Degree in Electrical Engineering or a closely related discipline.
Minimum 6 years of experience in Digital CMOS IC design and NVM/memory design.
Strong hands‑on experience with industry‑standard design, simulation, and physical implementation tools (e.g., Cadence DFII, Virtuoso, Spice simulators, Verilog‑A, Cadence Pegasus).
Solid understanding of CMOS technology, digital design principles, and the interaction between digital logic and analog/mixed‑signal blocks.
Experience with full design flow: architecture, RTL design, synthesis (if applicable), verification, physical implementation, and post‑silicon bring‑up.

Ideal fit

Previous DDR or other memory interface experience is a significant advantage.
Experience with 2.5D/3D IC design and packaging is highly valued.
Strong problem‑solving and debugging skills, with the ability to tackle complex cross‑domain issues.
Proven ability to work effectively in multidisciplinary, international teams.
Fluent in English, both written and spoken.
Strong interest in working in a start‑up environment, with high ownership, adaptability, and a hands‑on mindset.

About us

Ferroelectric Memory GmbH (FMC) is a pioneering semiconductor company based in Dresden, Germany, focused on next-generation non-volatile memory technology.
Founded in 2016, FMC is at the forefront of innovation in ferroelectric memory, enabling faster, more energy-efficient, and scalable solutions for future computing systems.

Our team combines deep expertise in semiconductor physics, device engineering, and system design to redefine memory architectures for emerging applications in AI, IoT, and high-performance computing.

Join us and be part of a team shaping the future of memory technology.

Why FMC?

Cutting-edge memory technology
Strong presence in the Dresden semiconductor ecosystem
High ownership and impact-driven roles
International and collaborative team
Direct contribution to AI and next-generation computing

Candidatura rapida

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quality ecosystem lead offerte - vimercate, lom

Senior Digital IC Design Engineer

Country Manager, BENELUX - Global Business Solutions - Amsterdam

Business Analytics Project Intern (TikTok Shop) - 2026 Start (BS/MS)

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