OUR STORY
At STMicroelectronics, we believe in the power of technology to drive innovation and make a positive impact on people, businesses, and society. As a global semiconductor company, our advanced technologies and chips form the hidden foundation of the world we live in today.
When you join ST, you will be part of a global business with more than 115 nationalities, present in 40 countries, and comprising over 50,000 diverse and dedicated creators and makers of technology around the world.
Developing technologies takes more than talent: it takes amazing people who understand collaboration and respect. People with passion and the desire to disrupt the status quo, drive innovation, and unlock their own potential.
Embark on a journey with us, where you can innovate for a future that we want to make smarter and greener, in a responsible and sustainable way. Our technology starts with you.
YOUR ROLE
The position is aimed at Mixed Signal verification engineer with previous experience in analog on top mixed simulations of ASIC.
The candidate will join the Mixed verification team of MEMS GROUP and will have the opportunity to see all the ASIC verification process from specification definition up to final product industrialization.
Your responsibilities include definition and development of verification test bench, development of verification components, test case development for simulation, debugging failures and creating simulation cases for various studies. As an experienced professional, work with the cutting-edge verification methodologies on Subsystem level and SoC level.
The position is open on both Castelletto (Italy) and Toulouse (France) sites. We are looking for Senior Profiles/Team Leader.
Your Skills & Experiences
The preferred seniority is 3 to 5 years of experience.
- The ideal candidate has a good knowledge of Analog custom circuit (e.g., ADC, DAC, comparators, ...), Analog, digital and mixed-signal simulation environments and tools, Bugs analysis and reporting, Analog SystemVerilog Assertions.
- Basic knowledge of Modeling languages such as System Verilog RNM, Verilog-AMS, Analog Model definition and implementation, Analog Model verification and validation, Coverage, Digital logic gates, Scripting languages like python, Unified Power Format (UPF) applied to mixed-signal simulations is a plus.
A plus will be considered the knowledge of SystemVerilog and UVM methodology, tools and environments for mixed-signal simulations Cadence based, Communication protocols in mixed simulations (e.g. I2C, SPI and I3C), Formal tools for top-level connectivity, Version control system.
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The candidate has also soft skills such as good communication, fluently in English, team working and collaboration across all the entire MEMS GROUP Design team.
ST is proud to be one of the 17 companies certified as a 2025 Global Top Employer and the first and only semiconductor company to achieve this distinction. ST was recognized in this ranking thanks to its continuous improvement approach and stands out particularly in the areas of ethics & integrity, purpose & values, organization & change, business strategy, and performance.
At ST, we endeavor to foster a diverse and inclusive workplace, and we do not tolerate discrimination. We aim to recruit and retain a diverse workforce that reflects the societies around us. We strive for equity in career development, career opportunities, and equal remuneration. We encourage candidates who may not meet every single requirement to apply, as we appreciate diverse perspectives and provide opportunities for growth and learning. Diversity, equity, and inclusion (DEI) is woven into our company culture.
To discover more, visit st.com/careers.
